Recently, data volume to be processed in an integrated circuit has increased. Therefore, a technology which increases efficiency of data transfer between blocks in an integrated circuit or between integrated circuits is desired. On the other hand, to enhance a data transfer function itself, various types of attribute information are transferred in addition to an address and data that are to be transferred.
To improve transfer efficiency, in Japanese Laid-Open Patent Application No. 2004-246694 (hereinafter referred to as “PTL 1”), a method is disclosed in which data transferred through a bus is compressed on a several bits basis. In Japanese Laid-Open Patent Application No. 2008-205942 (hereinafter referred to as “PTL 2”), a method is disclosed in which an address is compressed. In Japanese Laid-Open Patent Application No. 2009-135974 (hereinafter referred to as “PTL 3”), a method is disclosed in which a header including an address is compressed in a simple manner.
In the methods in PTLs 1 to 3, compression is achieved by utilizing redundancy. Accordingly, when randomness in values of transfer data or transfer addresses increases, the compression efficiency obtained by simply compressing addresses or headers is not good.